Parameterized Integer Divider:

The following custom divider cores are fully parameterized architectures. Three version are presented: one fully parallel for maximum performance, one fully combinatorial, and one iterative for minimum resources.

VHDL implementations (stand-alone IPs): Generic Pipelined Divider VHDL IPs
Report on Parameterized divider: (pdf)

Parameterized Pipelined Adder Tree :

The following custom Pipelined Adder Tree core (for signed numbers) is a fully parallel, fully pipelined, and fully parameterized architecture.

VHDL implementation (stand-alone IP): Generic Pipelined Adder Tree VHDL IP

Non restoring Square Root:

The following custom square root core is a fully optimized and parameterized architecture. Three versions are presented: one fully parallel for maximum performance, one purely combinatorial, and one iterative for minimum area. The core is based on a non-restoring algorithm described in:  Y. Li and W. Chu, "A New Non-Restoring Square Root Algorithm and its VLSI Implementations",  in Proceedings of the 1996 IEEE International Conference on Computer Designs, Austin, TX, Oct. 1996, pp. 538-544.

The core was presented in the following work:

• Llamocca, D., "A Core design to obtain square root based on a non-restoring algorithm", in Proceedings XI Workshop IBERCHIP , Salvador da Bahia, Brazil, March 2005.

VHDL implementation (stand-alone IP): Non restoring Square Root VHDL IP