Fall 2013 - Workshop: Digital Circuit Design with VHDL

Unit 1: Introduction

  • Slides: (pdf)
  • ISE: Design Entry (VHDL) + Simulation: (video)

VHDL Projects (VHDL file, testbench, and UCF file):
If UCF file is included, the NEXYS3 Development Boad is targeted

Unit 2: Concurrent Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 3: Behavioral Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 4:Structural Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 5: Sequential Circuits

VHDL Projects (VHDL file, testbench):
If UCF file is incluced, the NEXYS3 Development board is targeted

Unit 6: Finite State Machines

VHDL Projects (VHDL files, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 7: Introduction to Digital System Design

VHDL Projects (VHDL files, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 8: Introduction to Fixed-Point Arithmetic

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VHDL Projects (VHDL file, testbench, and UCF file):
UCF File: Targets the NEXYS3 Development Board

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