Fall 2013 - Workshop: Digital Circuit Design with VHDL

Fall 2013 - Workshop: Digital Circuit Design with VHDL

Unit 1: Introduction

VHDL Projects (VHDL file, testbench, and UCF file):
If UCF file is included, the NEXYS3 Development Boad is targeted

Unit 2: Concurrent Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 3: Behavioral Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 4:Structural Description

VHDL Projects (VHDL file, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Generic 2's complement Adder/Subtractor Unit (UCF included): (Project) (VHDL main file)
Arithmetic Logic Unit: (Project)
Generic Parallel Multiplier (unsigned): (Project) (VHDL main file)
4-bit Wallace Multiplier (unsigned): (Project)

Unit 5: Sequential Circuits

VHDL Projects (VHDL file, testbench):
If UCF file is incluced, the NEXYS3 Development board is targeted

BCD up/down counter with enable: (Project)
Modulo-13 counter with enable: (Project)
N-bit ring counter: (Project) (VHDL file)
N-bit register with enable: (Project) (VHDL file)
N-bit (right/left) shift register with enable: (Project) (VHDL file)
N-bit Parallel access (right/left) shift register with enable: (Project) (VHDL file)
N-bit counter with enable (Generic pulse generator with enable): (Project) (VHDL file)
LUT6to6 peripheral with 3-state buffers: (Project)

Unit 6: Finite State Machines

VHDL Projects (VHDL files, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 7: Introduction to Digital System Design

VHDL Projects (VHDL files, testbench):
If UCF file is included, the NEXYS3 Development Board is targeted

Unit 8: Introduction to Fixed-Point Arithmetic

VHDL Projects (VHDL file, testbench, and UCF file):
UCF File: Targets the NEXYS3 Development Board